Hardware-in-the-loop Simulation: a Scalable, Component-based, Time-triggered Hardware-in-the-loop Simulation Framework - Martin Schlager - 图书 - VDM Verlag Dr. Müller - 9783836462167 - 2008年4月21日
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Hardware-in-the-loop Simulation: a Scalable, Component-based, Time-triggered Hardware-in-the-loop Simulation Framework

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元 460
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预计送达时间 年6月5日 - 年6月23日
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Safety-critical real-time systems must guarantee correct operation in all operational conditions - even if these conditions are very unlikely to occur (rare events). Hardware-in-the-Loop (HiL) simulation is a common validation technique of real-time systems. In an HiL simulation the environment of a System-Under-Test (SUT) is simulated by an assigned HiL simulator. Thereby, the SUT interacts with the HiL simulator in real-time which necessitates a model of time and interfaces of the HiL simulator that are identical to the model of time and the interfaces of the SUT. In this book an HiL simulation framework is proposed that allows predictable interaction of a distributed HiL simulator and an SUT. This HiL simulation framework comprises configurable simulation components which are interconnected via a time-triggered interaction mechanism. Information flow between the HiL simulator and the SUT is strictly controlled by the progression of synchronized global time and bound to a priori known latency and jitter. This book addresses researchers and engineers in safety-critical domains such as the avionics or automotive industries.

介质类型 图书     Paperback Book   (平装胶订图书)
已发行 2008年4月21日
ISBN13 9783836462167
出版商 VDM Verlag Dr. Müller
页数 156
商品尺寸 150 × 220 × 10 mm   ·   213 g
语言 英语  

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